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US 2020/0006383 A1Published application
Content addressable memory using threshold-adjustable vertical transistors and methods of forming the same
AssigneeSanDisk Technologies LLC
InventorChristopher J. Petti
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Abstract
A content addressable memory cell is provided that includes a vertical transistor having a gate oxide that includes a ferroelectric material.
Claims20
A content addressable memory element comprising:
- a vertical transistor comprising a gate oxide comprising a ferroelectric material.
A content addressable memory cell array comprising:
- a plurality of match lines disposed in parallel along a first axis;
- a plurality of ground lines disposed in parallel along the first axis;
- a plurality of search lines disposed in parallel substantially perpendicular to the first axis;
- and
- a plurality of content addressable memory elements, each content addressable memory element comprising a vertical ferroelectric transistor disposed between a corresponding one of the match lines and a corresponding one of the ground lines, and each coupled to a corresponding one of the search lines.
2 more elements
A monolithic three-dimensional content addressable memory cell array comprising:
- a first memory level disposed above a substrate, the first memory level comprising:
- a plurality of first match lines disposed in parallel along a first axis;
- a plurality of first ground lines disposed in parallel along the first axis and above the plurality of first match lines;
- a plurality of first search lines disposed in parallel substantially perpendicular to the first axis;
- and
- a plurality of first content addressable memory elements, each first content addressable memory element comprising a vertical ferroelectric transistor disposed between a corresponding one of the first match lines and a corresponding one of the first ground lines, and each coupled to a corresponding one of the first search lines;
- and
- a second memory level disposed above the first memory level, the second memory level comprising:
- a plurality of second match lines disposed in parallel along the first axis and above the plurality of first ground lines;
- a plurality of second search lines disposed in parallel substantially perpendicular to the first axis;
- and
- a plurality of second content addressable memory elements, each second content addressable memory element comprising a vertical ferroelectric transistor disposed between a corresponding one of the second match lines and a corresponding one of the first ground lines, and each coupled to a corresponding one of the second search lines.
9 more elements
Dependencies are inferred from the claim text.