Three-dimensional memory device having a shielding layer and method for forming the same

A three-dimensional (3D) memory device, comprising:

• a substrate;
• a plurality of memory strings each extending vertically on the substrate;
• a peripheral device disposed above the plurality of memory strings;
• a semiconductor layer disposed above and in contact with the peripheral device;
• and
• a shielding layer disposed between the plurality of memory strings and the semiconductor layer, wherein the shielding layer comprises a conduction region configured to receive a grounding voltage during an operation of the 3D memory device.

A method for forming a three-dimensional (3D) memory device, comprising:

• forming a peripheral device on a first substrate;
• forming, on the first substrate, a first interconnect layer comprising a plurality of interconnect structures above the peripheral device;
• forming, on the first substrate, a shielding layer comprising a conduction region above the first interconnect layer, wherein the conduction region of the shielding layer covers substantially an area of the plurality of interconnect structures in the first interconnect layer;
• forming, on a second substrate, an alternating conductor/dielectric stack and a plurality of memory strings each extending vertically through the alternating conductor/dielectric stack;
• forming, on the second substrate, a second interconnect layer comprising a plurality of interconnect structures above the plurality of memory strings;
• and
• bonding the first substrate and the second substrate in a face-to-face manner, such that the shielding layer is between the first interconnect layer and the second interconnect layer.

A method for forming a three-dimensional (3D) memory device, comprising:

• forming, on a first substrate, an alternating conductor/dielectric stack and a plurality of memory strings each extending vertically through the alternating conductor/dielectric stack;
• forming, on the first substrate, a first interconnect layer comprising a plurality of interconnect structures above the plurality of memory strings;
• forming, on the first substrate, a shielding layer comprising a conduction region above the first interconnect layer, wherein the conduction region of the shielding layer covers substantially an area of the plurality of interconnect structures in the first interconnect layer;
• forming a peripheral device on a second substrate;
• forming, on the second substrate, a second interconnect layer comprising a plurality of interconnect structures above the peripheral device;
• and
• bonding the first substrate and the second substrate in a face-to-face manner, such that the shielding layer is between the first interconnect layer and the second interconnect layer.