Embedded memory using soi structures and methods

An integrated circuit (IC) including a memory device, comprising:

• a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer;
• first and second individual source/drain regions arranged in the semiconductor device layer and spaced apart from one another;
• first and second intermediate source/drain regions arranged in the semiconductor device layer and arranged between the first and second individual source/drain regions, the first individual source/drain region being spaced apart from the first intermediate source/drain region by a first control channel region, and the second individual source/drain region being spaced apart from the second intermediate source/drain region by a second control channel region;
• a common source/drain region arranged in the semiconductor device layer and arranged between the first and second intermediate source/drain regions, the first intermediate source/drain region being spaced apart from the common source/drain region by a first select channel region, and the second intermediate source/drain region being spaced apart from the common source/drain region by a second select channel region;
• first and second control gates arranged over the first and second control channel regions, respectively;
• and
• first and second select gates arranged over the first and second select channel regions, respectively;
• wherein the common source/drain region includes a doped region arranged in the handle substrate and an epitaxial semiconductor region extending from near an upper surface of the semiconductor device layer to an upper surface of the doped region.

An integrated circuit (IC) including a memory device, comprising:

• a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, a silicon dioxide insulator layer over the handle substrate, and a monocrystalline silicon device layer over the silicon dioxide insulator layer;
• first and second individual source/drain regions arranged in the monocrystalline silicon device layer and spaced apart from one another;
• first and second intermediate source/drain regions arranged in the monocrystalline silicon device layer and arranged between the first and second individual source/drain regions, the first individual source/drain region being spaced apart from the first intermediate source/drain region by a first control channel region, and the second individual source/drain region being spaced apart from the second intermediate source/drain region by a second control channel region;
• first and second control gates arranged over the first and second control channel regions, respectively;
• and
• first and second charge trapping dielectric structures arranged under the first and second control gates, respectively, the first and second charge trapping dielectric structures being configured to retain charge levels indicative of first and second data states;
• a common source/drain region arranged in the monocrystalline silicon device layer and arranged between the first and second intermediate source/drain regions, the first intermediate source/drain region being spaced apart from the common source/drain region by a first select channel region, and the second intermediate source/drain region being spaced apart from the common source/drain region by a second select channel region;
• first and second select gates arranged over the first and second select channel regions, respectively;
• wherein the common source/drain region includes a doped region arranged in the handle substrate and an epitaxial silicon region extending from near an upper surface of the monocrystalline silicon device layer to an upper surface of the doped region.