Sonos nonvolatile memory and method for manufacturing same

A method for manufacturing a SONOS nonvolatile memory, wherein cell structures of a SONOS nonvolatile memory each comprises a memotron and a selectron, and the method comprises the following steps:

• Step 1, sequentially forming an ONO layer, a first polysilicon layer and a second silicon oxide layer on a surface of a semiconductor substrate;
• Step 2, photo-etching the second silicon oxide layer to form first windows;
• Step 3, forming first top silicon nitride layers on two inner sides of each said first window through silicon nitride growth and full etching;
• Step 4, etching a portion, between every two said corresponding first top silicon nitride layers, of the first polysilicon layer for the first time to form second sides of first polysilicon gates of two said adjacent memotrons;
• wherein, a first gate structure of the memotron of each said cell structure comprises one said ONO layer, one said first polysilicon layer and one said first top silicon nitride layer which are sequentially stacked on the surface of the semiconductor substrate;
• two said adjacent cell structures form a cell structure combination, wherein in the cell structure combination, second sides of the first gate structures of the two cell structures are adjacent to each other, and the second sides of the first polysilicon gates and second sides of the first top silicon nitride layers are stacked together to form second sides of the first gate structures;
• Step 5, forming first silicon nitride spacers on the second sides of the first gate structures through self-alignment by means of silicon nitride growth and full etching;
• Step 6, carrying out source-drain implantation for the first time to form a first source-drain region in a portion, between the two first silicon nitride spacers in the cell structure combination, of the semiconductor substrate through self-alignment, wherein the first source-drain region is shared by the two cell structures of the corresponding cell structure combination;
• Step 7, filling an area between the two first silicon nitride spacers at the top of each said first source-drain region with an organic anti-reflection coating;
• Step 8, removing the second silicon oxide layer to expose first sides of the first top silicon nitride layers;
• Step 9, etching the first polysilicon layer for the second time to form first sides of the first polysilicon gates of the corresponding memotrons, wherein the first sides of the first polysilicon gates and the first sides of the first top silicon nitride layers are self-aligned and stacked together to form first sides of the first gate structures;
• Step 10, removing the organic anti-reflection coating, forming an inter-gate dielectric isolation layer on the first sides of the gate structures through self-alignment by means of deposition and full etching, removing a portion, outside the first side of the inter-gate dielectric isolation layer, of the ONO layer, and filling an area between the two first silicon nitride spacers at the top of each said first source-drain region with an inter-gate dielectric isolation layer formed on the second sides of the first gate structures;
• Step 11, sequentially forming a gate dielectric layer and a second polysilicon layer, and fully etching the second polysilicon layer to form second polysilicon gates on a first side of the inter-gate dielectric isolation layer through self-alignment, wherein a second gate structure of each said selectron comprises one said gate dielectric layer and one said second polysilicon gate which are sequentially stacked on the surface of the semiconductor substrate;
• Step 12, with first sides of the second gate structure as self-alignment boundaries, source-drain implantation is carried out for the second time to form second source-drain regions in portions, outside the first sides of the corresponding second gate structures, of the semiconductor substrate;
• and
• Step 13, forming an interlayer film and contact holes, wherein the contact holes penetrate through the interlayer film, and a bottom area of a first contact hole in a top of each said first source-drain region is defined through self-alignment by second sides of the two first silicon nitride spacers in the corresponding cell structure combination.