Stacked nanosheet field effect transistor floating-gate eeprom cell and array

A memory array, comprising:

• an N by M array of memory cells, wherein N represents the number of rows and M represents the number of columns each memory cell comprising:
• a first nanosheet transistor connected to a first terminal;
• a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal;
• and
• N access transistors, with one of the N access transistors located in each row of the array, wherein each access transistor is connected in series to a low voltage terminal and the common output terminals of M memory cells in a row, and wherein the access transistors are configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.

A method of forming a memory cell in a memory array formed from an N by M array of memory cells, the method comprising:

• connecting a first nanosheet transistor to a first terminal;
• connecting a second nanosheet transistor located on top of the first nanosheet transistor, connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal;
• and
• connecting an access transistor in series to the common output terminal and to a low voltage terminal, wherein the access transistor is configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.