US 2020/0006361 A1Published application

Erasable programmable non-volatile memory

AssigneeeMemory Technology Inc.

InventorChia-Jung HSU

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Abstract

An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. The second select transistor also includes the select gate. A first source/drain terminal of the second select transistor receive a second source line voltage. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.

Claims21

Dependent claims

An erasable programmable non-volatile memory, comprising:

a first select transistor comprising a select gate, a first source/drain terminal and a second source/drain terminal, wherein the select gate of the first select transistor receives a select gate voltage, and the first source/drain terminal of the first select transistor receives a first source line voltage;
a first floating gate transistor comprising a floating gate, a first source/drain terminal and a second source/drain terminal, wherein the first source/drain terminal of the first floating gate transistor is connected with the second source/drain terminal of the first select transistor, and the second source/drain terminal of the first floating gate transistor receives a first bit line voltage;
a second select transistor comprising the select gate, a first source/drain terminal and a second source/drain terminal, wherein the first source/drain terminal of the second select transistor receives a second source line voltage;
and
a second floating gate transistor comprising the floating gate, a first source/drain terminal and a second source/drain terminal, wherein the first source/drain terminal of the second floating gate transistor is connected with the second source/drain terminal of the second select transistor, and the second source/drain terminal of the second floating gate transistor receives a second bit line voltage,
wherein the first select transistor and the first floating gate transistor are constructed in a first well region, the second select transistor and the second floating gate transistor are constructed in a second well region, and the first well region and the second well region have different types.

3 more elements

An erasable programmable non-volatile memory, comprising:

a semiconductor layer;
a first well region formed in the semiconductor layer;
a first doped region, a second doped region and a third doped region, which are formed in a surface of the first well region, wherein the first doped region receives a first source line voltage, and the third doped region receives a first bit line voltage;
a second well region formed in the semiconductor layer;
a fourth doped region, a fifth doped region and a sixth doped region, which are formed in a surface of the second well region, wherein the fourth doped region receives a second source line voltage, and the sixth doped region receives a second bit line voltage;
a select gate spanned over an area between the first doped region and the second doped region and an area between the fourth doped region and the fifth doped region, wherein the select gate receives a select gate voltage;
a floating gate spanned over an area between the second doped region and the third doped region and an area between the fifth doped region and the sixth doped region;
and
an isolation structure formed in the semiconductor layer and arranged between the first well region and the second well region.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/397,143Filed 29 Apr 2019
Priority: 27 Jun 2018
Published: 2 Jan 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification24 codes

G11C 16/0425
Comprising cells containing floating gate transistors: comprising cells containing a merged floating gate and select transistor
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
G11C 16/0416
Comprising cells containing floating gate transistors: comprising cells containing a single floating gate transistor and no select transistor,…
G11C 16/0433
Comprising cells containing floating gate transistors: comprising cells containing a single floating gate transistor and one or more separate…