Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same

A method of forming a three-dimensional memory device, comprising:

• forming an alternating stack of insulating layers and word-line-level spacer material layers over a substrate, wherein the word-line-level spacer material layers are formed as, or are subsequently replaced with, word-line-level electrically conductive layers;
• forming memory stack structures through the alternating stack, wherein each memory stack structure comprises a respective word-line-level semiconductor channel portion and a respective memory film;
• forming drain-select-level sacrificial material layers spaced apart by drain-select-level insulating layers over the alternating stack;
• forming drain-select-level sacrificial line structures through the drain-select-level sacrificial material layers and the drain-select-level insulating layers;
• forming drain-select-level backside recesses adjoined to drain-select-level isolation trenches by removing portions of the drain-select-level sacrificial line structures and the drain-select-level sacrificial material layers;
• and
• forming a plurality of multi-level drain select electrodes comprising a respective vertical connection portion adjoined to respective set of drain-select-level electrically conductive layers within volumes of the drain-select-level backside recesses and the drain-select-level isolation trenches.