Ferroelectric-capacitor integration using novel multi-metal-level interconnect with replaced dielectric for ultra-dense embedded sram in state-of-the-art cmos technology

A method of forming a memory array, comprising:

• disposing a first dielectric layer over first metal traces, wherein the first metal traces extend along a first direction;
• disposing second metal traces on the first dielectric layer, wherein the second metal traces extend along a second direction that is perpendicular to the first direction;
• disposing third metal traces on the second dielectric layer, wherein the third metal traces extend along the first direction;
• forming a trench through the third metal traces, the second dielectric layer, the second metal traces, and the first dielectric layer, wherein the trench includes one or more sidewalls and a bottom surface above a first metal trace, wherein the trench has a depth defined from a top surface of the first metal trace to the top surface of the third metal trace, and wherein the trench is self-aligned by the third metal traces and the second metal traces;
• and
• disposing an insulating sidewall layer, a first electrode layer, a ferroelectric layer, and a second electrode layer, respectively, into the trench to form a ferroelectric capacitor, wherein the trench of the ferroelectric capacitor has a rectangular cylinder shape that is defined by the first, second, and third metal traces.

A memory device, comprising:

• a semiconductor substrate;
• a memory array above the semiconductor substrate;
• and
• a plurality of ferroelectric capacitors integrated into the memory array, wherein the memory array includes
• a first dielectric layer over first metal traces, wherein the first metal traces extend along a first direction;
• second metal traces on the first dielectric layer, wherein the second metal traces extend along a second direction that is perpendicular to the first direction;
• third metal traces on the second dielectric layer, wherein the third metal traces extend along the first direction;
• the plurality of ferroelectric capacitors positioned in a plurality of trenches, wherein a trench of the plurality of trenches includes one or more sidewalls and a bottom surface above a first metal trace, wherein the trench has a depth defined from a top surface of the first metal trace to the top surface of the third metal trace;
• and
• an insulating sidewall layer, a first electrode layer, a ferroelectric layer, and a second electrode layer disposed in the trench of the ferroelectric capacitor, wherein the trench of the ferroelectric capacitor has a rectangular cylinder shape that is defined by the first, second, and third metal traces.