Techniques for Enhancing Vertical Gate-All-Around FET Performance

A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:

• patterning at least one n-channel field-effect transistor (NFET) fin and at least one p-channel FET (PFET) fin in a substrate;
• forming NFET bottom source and drains at a base of the at least one NFET fin and PFET bottom source and drains at a base of the at least one PFET fins;
• forming bottom spacers on the NFET and PFET bottom source and drains;
• forming gates along sidewalls of the at least one NFET fin and along sidewalls of the at least one PFET fin;
• recessing the gates to expose top portions of the at least one NFET fin and the at least one PFET fin;
• forming an oxide layer along the sidewalls of the top portions of the at least one NFET fin and the at least one PFET fin;
• selectively forming a positively charged layer over the at least one NFET fin in contact with the oxide layer along the sidewalls of the top portions of the at least one NFET fin, wherein the positively charged layer induces a negative charge in the top portion of the at least one NFET fin forming a first dipole;
• selectively forming a negatively charged layer over the at least one PFET fin in contact with the oxide layer along the sidewalls of the top portions of the at least one PFET fin, wherein the negatively charged layer induces a positive charge in the top portion of the at least one PFET fin forming a second dipole;
• forming top spacers above the gate;
• and
• forming NFET and PFET top source and drains above the top spacers.