Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsGuyoung CHO, Subin SHIN, DONGHYUN ROH, Byung-Suk JUNG, SANGJIN HYUN
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Abstract
Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.
Claims20
A semiconductor device, comprising:
- a substrate;
- a plurality of active patterns that protrude with respect to the substrate;
- a device isolation layer between the active patterns;
- and
- a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns,
- wherein the device isolation layer includes:
- a plurality of first isolation parts adjacent to facing sidewalls of the active patterns;
- and
- a second isolation part between the first isolation parts,
- wherein a top surface of the second isolation part is located at a lower vertical level than top surfaces of the first isolation parts.
A semiconductor device, comprising:
- a substrate that includes a plurality of active patterns extending lengthwise in a first direction;
- a gate electrode that runs across the active pattern and extends lengthwise in a second direction;
- a device isolation layer that fills a gap between the active patterns;
- a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns;
- and
- a gate dielectric layer between the gate electrode and the active patterns and between the gate electrode and the passivation layer,
- wherein the passivation layer includes a plurality of first segments and a second segment between two first segments of the plurality of first segments,
- wherein a top surface of the second segment is located at a lower vertical level than top surfaces of each of the two first segments.
A semiconductor device, comprising:
- a substrate that includes a first active pattern and a second active pattern;
- a device isolation layer that fills a gap between the first and second active patterns;
- a passivation layer that is disposed on the device isolation layer and exposes an upper portion of the first active pattern and an upper portion of the second active pattern;
- a first source/drain pattern at the upper portion of the first active pattern;
- and
- a second source/drain pattern at the upper portion of the second active pattern,
- wherein the passivation layer includes a first segment and a second segment,
- wherein a top surface of the second segment is located at a lower vertical level than a top surface of the first segment, and
- wherein a bottom surface of at least one of the first and second active patterns cover at least a portion of the top surface of the first segment.
Dependencies are inferred from the claim text.