Channel structures with sub-fin dopant diffusion blocking layers

An integrated circuit structure, comprising:

• a fin comprising a lower fin portion and an upper fin portion, the lower fin portion comprising a layer comprising carbon, the layer comprising carbon on an N-type doped semiconductor layer, and the upper fin portion comprising a portion of a semiconductor layer comprising germanium, the semiconductor layer comprising germanium on the layer comprising carbon;
• an isolation structure along sidewalls of the lower fin portion;
• a gate stack over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side, and the gate stack comprising a P-type gate electrode;
• a first source or drain structure at the first side of the gate stack;
• and
• a second source or drain structure at the second side of the gate stack, wherein the first and second source or drain structures are first and second P-type source or drain structures.

An integrated circuit structure, comprising:

• a fin comprising a lower fin portion and an upper fin portion, the lower fin portion comprising a layer comprising carbon, the layer comprising carbon on a P-type doped semiconductor layer, and the upper fin portion comprising a portion of a semiconductor layer comprising a Group III-V material, the semiconductor layer comprising the Group III-V material on the layer comprising carbon;
• an isolation structure along sidewalls of the lower fin portion;
• a gate stack over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side, and the gate stack comprising an N-type gate electrode;
• a first source or drain structure at the first side of the gate stack;
• and
• a second source or drain structure at the second side of the gate stack, wherein the first and second source or drain structures are first and second N-type source or drain structures.