Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure

An integrated circuit structure, comprising:

• a fin structure including an upper portion in the form of a fin, nanowire, or nanoribbon and a lower portion in the form of a fin, nanowire, or nanoribbon, wherein sidewalls of the upper portion are collinear with sidewalls of the lower portion;
• a first gate structure at least on the sidewalls of the upper portion, the first gate structure including a first gate electrode and a first gate dielectric, the first gate dielectric between the first gate electrode of the upper portion, the first gate electrode including a first metal, and the first gate dielectric having a first thickness;
• a first source region and a first drain region adjacent the first gate structure;
• a second gate structure on the sidewalls of the lower portion, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric between the second gate electrode and the lower portion, the second gate electrode including a second metal that is compositionally different from the first metal, and the second gate dielectric having a second thickness that is at least 1 nm different from the first thickness;
• and
• a second source region and a second drain region adjacent the second gate structure.