Back to results
US 2020/0006306 A1Published application
Configurable random-access memory (ram) array including through-silicon via (tsv) bypassing physical layer
AssigneeShanghai Denglin Technologies Co., Ltd.
InventorJianwen Li
Life of this patent
Estimating the term…
Abstract
A system comprising a main logic circuit comprising a memory controller comprising a signal control circuit and a through-silicon via (TSV) connection point electrically coupled to the signal control circuit, and a memory device comprising a memory unit comprising a TSV electrically coupled to the TSV connection point of the main logic circuit, wherein the signal control circuit is to transmit a signal using the TSV to operate the memory device.
Claims20
A system comprising:
- a main logic circuit comprising:
- a memory controller comprising a signal control circuit;
- and
- a through-silicon via (TSV) connection point electrically coupled to the signal control circuit;
- and
- a memory device comprising a memory unit comprising a TSV electrically coupled to the TSV connection point of the main logic circuit, wherein the signal control circuit is to transmit a signal using the TSV to operate the memory device.
3 more elements
A memory device, comprising:
- a memory structure comprising a memory unit, the memory unit comprising a through-silicon via (TSV) coupled to a TSV connection point of a main logic circuit, wherein a signal control circuit of the main logic is to transmit a signal using the TSV to operate the memory device.
A method comprising:
- fabricating a main logic circuit comprising a memory controller and a pre-determined number of memory unit receptors;
- fabricating a plurality of memory units, each comprising a plurality of through-silicon vias (TSVs);
- determining, by a processing device based on a system specification, a number of memory structures, wherein each memory structure is to hold the pre-determined number of memory units;
- and
- bonding the determined number of memory structures to the main logic circuit by matching the pre-determined number of memory units to the pre-determined number of memory unit receptors, forming, using the plurality of TSVs, signal paths between the memory controller and the plurality of memory units bypassing a memory physical layer.
2 more elements
Dependencies are inferred from the claim text.