Chip scale thin 3d die stacked package
AssigneeIntel Corporation
InventorsRobert SANKMAN, Sanka GANESAN, Bernd WAIDHAS, Thomas WAGNER, Lizabeth KESER
Life of this patent
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Abstract
Embodiments disclosed herein include an electronics package comprising stacked dies. In an embodiment, the electronics package comprises a first die that includes a plurality of first conductive interconnects extending out from a first surface of the first die. In an embodiment, the first die further comprises a keep out zone. In an embodiment, the electronic package may also comprise a second die. In an embodiment, the second die is positioned entirely within a perimeter of the keep out zone of the first die. In an embodiment, a first surface of the second die faces the first surface of the first die.
Claims25
An electronics package, comprising:
- a first die, wherein the first die comprises a plurality of first conductive interconnects extending out from a first surface of the first die, and wherein the first die comprises a keep out zone;
- and
- a second die, wherein the second die is positioned entirely within a perimeter of the keep out zone of the first die, and wherein a first surface of the second die faces the first surface of the first die.
An electronics package, comprising:
- a first die, wherein the first die comprises a keep out zone;
- a second die, wherein a first surface of the first die faces a first surface of the second die, and wherein the second die is positioned within a perimeter of the keep out zone of the first die;
- and
- a third die, wherein the third die comprises a plurality of conductive pillars extending out from a first surface of the third die, and wherein the conductive pillars electrically couple the third die to the first die.
A computer system, comprising:
- a first die;
- a second die communicatively coupled to the first die, wherein a first surface of the first die faces a first surface of the second die;
- a third die, wherein a first surface of the third die faces a first surface of the first die, and wherein the third die is electrically coupled to the first die by a plurality of conductive pillars;
- and
- a plurality of second level interconnects electrically coupled to the first surface of the first die, wherein the second die and the third die are positioned between the first surface of the first die and the second level interconnects.
Dependencies are inferred from the claim text.