Semiconductor memory device

A semiconductor memory device comprising:

• peripheral circuit elements defined on a first substrate;
• a first dielectric layer covering the peripheral circuit elements;
• a plurality of first pads exposed at a top surface of the first dielectric layer, and coupled with the peripheral circuit elements;
• a second substrate disposed on a base dielectric layer;
• a memory cell array defined on the second substrate;
• a second dielectric layer covering the second substrate and the memory cell array;
• a third dielectric layer disposed on the second dielectric layer, and having one surface which is bonded with the top surface of the first dielectric layer;
• a plurality of second pads exposed at the one surface of the third dielectric layer, and coupled with the first pads;
• a contact passing through the base dielectric layer and the second dielectric layer;
• and
• one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.