Semiconductor package having redistribution layer
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung Kun JEE, II Hwan KIM, Un Byoung KANG
Life of this patent
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Abstract
A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.
Claims20
A semiconductor package comprising:
- a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity;
- a first semiconductor chip in the cavity;
- a plurality of conductive vias in the plurality of through holes;
- a first redistribution layer on the silicon substrate, the first redistribution layer connected to the first semiconductor chip and the plurality of conductive vias;
- and
- a second redistribution layer below the silicon substrate, the second redistribution layer connected to the first semiconductor layer and the plurality of conductive vias.
A semiconductor package comprising:
- a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity;
- a first semiconductor chip in the cavity;
- a plurality of conductive vias in the plurality of through holes;
- a first redistribution layer on the silicon substrate, the first redistribution layer connected to the first semiconductor chip and the plurality of conductive vias;
- a second redistribution layer below the silicon substrate, the second redistribution layer connected to the first semiconductor chip and the plurality of conductive vias;
- and
- a second semiconductor chip on the first redistribution layer, the second semiconductor chip connected to the first redistribution layer.
A semiconductor package comprising:
- a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity;
- a first semiconductor chip in the cavity;
- a first redistribution layer on the silicon substrate;
- a second redistribution layer below the silicon substrate, the second redistribution layer connected to the first semiconductor chip;
- a second semiconductor chip on the first redistribution layer, the second semiconductor chip connected to the first redistribution layer;
- a third semiconductor chip on the first semiconductor chip, the third semiconductor chip connected to the first redistribution layer;
- and
- a plurality of conductive vias in the plurality of through holes.
Dependencies are inferred from the claim text.