3d ic decoupling capacitor structure and method for manufacturing the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWEN-SHIANG LIAO, CHEWN-PU JOU
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Abstract
A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer; a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.
Claims20
A method for manufacturing a semiconductor structure, comprising:
- providing a base layer;
- forming a photoresist layer over the base layer, the photoresist layer having an opening;
- blanket disposing a first conductive layer over the photoresist layer;
- blanket disposing an insulation layer over the conductive layer;
- etching a portion of the insulation layer to expose a portion of the first conductive layer outside the opening;
- disposing a second conductive layer over the insulation layer and the exposed first conductive layer;
- planarizing the second conductive layer until the photoresist layer is exposed;
- and
- removing the photoresist layer, wherein the first conductive layer, the insulation layer and the second conductive layer form a metal-insulator-metal (MIM) capacitor.
A method for manufacturing a semiconductor structure, comprising:
- providing a polymer base layer;
- forming a redistribution layer (RDL) over the polymer base layer;
- forming a photoresist layer having an opening passing through the photoresist layer over the RDL;
- forming a metal-insulator-metal (MIM) capacitor vertically passing through the photoresist layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein an outer sidewall and an outer bottom surface of the first electrode is lined with the insulation layer, and an outer sidewall and an outer bottom surface of the insulation layer is lined with the second electrode;
- performing a CMP upon the MIM capacitor and the photoresist layer;
- and
- removing the photoresist layer.
A method for manufacturing a semiconductor structure, comprising:
- providing a polymer base layer;
- forming a first redistribution layer (RDL) over the polymer base layer;
- forming a photoresist layer having an opening passing through the photoresist layer over the first RDL;
- blanket disposing a first conductive layer over the photoresist layer and the first RDL;
- blanket disposing an insulation layer over the conductive layer;
- etching a portion of the insulation layer to expose a portion of the first conductive layer outside the opening;
- disposing a second conductive layer over the insulation layer and the exposed first conductive layer;
- and
- planarizing the second conductive layer until the photoresist layer is exposed.
Dependencies are inferred from the claim text.