Warpage control of semiconductor die
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYun-Ting WANG, Yi-An LIN, Ching-Chuan CHANG, Po-Chang KUO
Life of this patent
Estimating the term…
Abstract
A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.
Claims20
A method, comprising:
- forming a bottom passivation layer on a dielectric layer over a semiconductor substrate;
- forming a first opening in the bottom passivation layer to expose a portion of the dielectric layer;
- forming a metal pad in the first opening;
- forming a first oxide-based passivation layer over the metal pad;
- and
- forming a second oxide-based passivation layer over the first oxide-based passivation layer, the second oxide-based passivation layer having a hardness less than a hardness of the first oxide-based passivation layer.
A method, comprising:
- forming a bottom passivation layer on a dielectric layer over a semiconductor substrate;
- forming a first opening in the bottom passivation layer to expose a portion of the dielectric layer;
- forming a metal pad in the first opening and over the bottom passivation layer;
- depositing a first oxide-based passivation layer over the metal pad at a first deposition rate;
- and
- depositing a second oxide-based passivation layer over the first oxide-based passivation layer at a second deposition rate faster than the first deposition rate.
A semiconductor die, comprising:
- a semiconductor substrate;
- a dielectric layer over the semiconductor substrate;
- a metal structure in the dielectric layer;
- a first metal pad over the metal structure;
- a first oxide-based passivation layer over the first metal pad;
- a second oxide-based passivation layer over the first oxide-based passivation layer and having a hardness less than a hardness of the first oxide-based passivation layer;
- and
- a bump electrically connected to the first metal pad.
Dependencies are inferred from the claim text.