Conductive vias in semiconductor packages and methods of forming same

A semiconductor package comprising:

• a first semiconductor die bonded to an interposer, the interposer comprising a substrate;
• a second semiconductor die bonded to the interposer and adjacent the first semiconductor die, wherein a metallization line in the interposer electrically connects the first semiconductor die to the second semiconductor die;
• an encapsulant encapsulating the first semiconductor die and the second semiconductor die;
• a first silicon-comprising insulating material on a surface of the substrate opposite the first semiconductor die and the second semiconductor die;
• and
• a through via extending through the first silicon-comprising insulating material and the substrate to the metallization line, wherein the through via is separated from the substrate by a second silicon-comprising insulating material, and a sidewall of the first silicon-comprising insulating material touches a sidewall of the second silicon-comprising insulating material.

A package comprising:

• a first die and a second die bonded to a substrate, the substrate is free of active devices;
• a silicon nitride layer on an opposing surface of the substrate as the first die;
• a polymer layer on an opposing surface of the silicon nitride layer as the substrate;
• a through via extending through the polymer layer, the silicon nitride layer, and the substrate, wherein the through via is electrically connected to the first die and the second die by a metallization line;
• and
• a silicon nitride spacer insulating the through via from the substrate, wherein the silicon nitride spacer forms an interface with the silicon nitride layer, and the interface is between the through via and the substrate.