Integrated Circuit with Airgaps to Control Capacitance

4:

• The system of claim 1 wherein:
• the conformal layer directly contacts a first surface of the additional layer;
• a second surface of the additional layer directly contacts the first interconnect layer;
• the first and second surfaces of the additional layer directly oppose one another.

8:

• The system of claim 7 comprising:
• a first layer that includes a dielectric material;
• a second layer that includes the dielectric material;
• a third layer that includes the dielectric material;
• wherein:
• (a) the second interconnect layer is between the first layer that includes the dielectric material and the second layer that that includes the dielectric material;
• and (b) the third interconnect layer is between the second layer that includes the dielectric material and the third layer that includes the dielectric material.

9:

• The system of claim 8, wherein:
• the dielectric material has a first etch rate corresponding to an etchant, the etchant including carbon and fluorine;
• the additional layer has a second etch rate corresponding to the etchant;
• the first etch rate is at least 15 times greater than the second etch rate.

10:

• The system of claim 9 comprising another layer between the additional layer and the first layer that includes the dielectric material, wherein:
• the another layer has a third etch rate corresponding to the etchant;
• the first etch rate is greater than the third etch rate;
• the second etch rate is less than the third etch rate.

11:

• The system of claim 10, wherein:
• the second axis intersects the first void;
• the second axis does not intersect the another layer;
• the second axis does not intersect the first layer that includes the dielectric material;
• the third axis intersects the another layer.

12:

• The system of claim 8 wherein:
• a portion of the first layer that includes the dielectric material is between the additional layer and the second interconnect line;
• the conformal layer directly contacts the portion;
• the conformal layer directly contacts the second void.

14:

• The system of claim 8 comprising a via, wherein:
• the via couples the first interconnect layer to the first interconnect line;
• the via has a height measured orthogonal to the first axis and extending from the first interconnect layer to the first interconnect line;
• a portion of dielectric material of the first layer that includes the dielectric material surrounds the via in a plane that is parallel to the first axis;
• the portion has a height, measured orthogonal to the first axis, of at least 50% of the height of the via;
• the first void extends from the second layer that includes the dielectric material to a first half of the via, wherein the first half of the via is between a second half of the via and the first interconnect layer.

15:

• The system of claim 2 wherein:
• the second interconnect line is the only interconnect line located between the first and third interconnect lines in a plane that is parallel to both of the first and second axes;
• the first and second interconnect lines are separated from each other by a first width taken along the first axis;
• the second and third interconnect lines are separated from each other by a second width taken along the second axis;
• the second width is at least two times the first width.

16:

• The system of claim 15 wherein:
• a fourth axis is orthogonal to the first axis;
• the fourth axis intersects the second void, the conformal layer, and the additional layer;
• the conformal layer directly contacts the second void;
• the conformal layer directly contacts the additional layer at a first location;
• the additional layer directly contacts the first interconnect layer at a second location;
• the fourth axis intersects the first and second locations;
• and
• the fourth axis is between the second and third interconnect lines.

19:

• The system of claim 1 comprising:
• an integrated circuit;
• a memory;
• and
• a package housing that includes the integrated circuit and the memory;
• wherein one of the integrated circuit and the memory includes the first and second voids.

21:

• The system of claim 19 comprising:
• a radiofrequency receiver;
• and
• a chassis;
• wherein the chassis includes the radiofrequency receiver and the package.

22:

• A method comprising:
• forming a layer of transistors;
• forming a first interconnect layer on the layer of transistors, the first interconnect layer including a metal;
• forming an additional layer on the first interconnect layer;
• forming a first layer that includes a dielectric material, wherein forming the first layer that includes the dielectric material includes forming the first layer that includes the dielectric material on the additional layer;
• forming a first interconnect line in a second interconnect layer, wherein the first interconnect line includes the metal, the second interconnect layer includes the metal, and the second interconnect layer is formed on the first interconnect layer;
• forming a second interconnect line in the second interconnect layer, wherein the second interconnect line includes the metal;
• etching a void in the first layer that includes the dielectric material, the void extending from a top of the first interconnect line to a top of the additional layer;
• in response to etching the void in the first layer that includes the dielectric material, leaving a portion of the first layer that includes the dielectric material between the first interconnect line and the additional layer;
• forming a conformal layer on a bottom and opposing sidewalls of the void;
• forming a second layer that includes the dielectric material, wherein forming the second layer that includes the dielectric material includes forming the second layer that includes the dielectric material on the second interconnect layer;
• in response to forming the second layer that includes the dielectric material on the second interconnect layer, enclosing air within the void so the void is hollow;
• forming a third interconnect layer on the second layer that includes the dielectric material, wherein the third interconnect layer includes the metal;
• wherein (a) a first axis intersects the first and second interconnect lines and the void;
• (b) a second axis, orthogonal to the first axis, intersects the conformal layer and the additional layer;
• and (c) a third axis, orthogonal to the first axis, intersects the second interconnect line and the additional layer.

23:

• The method of claim 22, wherein:
• the additional layer includes at least one of oxygen, nitrogen, carbon, or combinations thereof;
• the additional layer further includes at least one of aluminum, hafnium, or combinations thereof;
• the conformal layer directly contacts the additional layer;
• and
• the conformal layer directly contacts the void.

24:

• An integrated circuit system comprising:
• first, second, and third interconnect wires included in a buildup layer;
• a first void between the first and second interconnect wires and a second void between the second and third interconnect wires;
• a conformal layer between the first and second interconnect wires;
• and
• an additional layer between the first interconnect wire and a substrate that includes transistors;
• wherein the first and second voids are hollow and include air;
• wherein (a) a first axis intersects the first, second, and third interconnect wires and the first and second voids;
• (b) a second axis, orthogonal to the first axis, intersects the conformal layer and the additional layer;
• and (c) a third axis, orthogonal to the first axis, intersects the second interconnect wire and the additional layer;
• wherein the conformal layer directly contacts the additional layer.