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US 2020/0006114 A1Published application
Negatively Sloped Isolation Structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsGulbagh Singh, Tsung-Han Tsai, Kun-Tsang Chuang
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Abstract
Negatively sloped isolation structures are formed on a semiconductor substrate to isolate devices from one another. The negatively sloped isolation structures have a top critical dimension which is smaller than a bottom critical dimension. The negatively sloped isolation structures may penetrate through an insulator layer of a silicon-on-insulator structure arrangement.
Claims20
A structure comprising:
- a semiconductor material layer;
- a first isolation structure embedded in the semiconductor material layer;
- a second isolation structure embedded in the semiconductor material layer, wherein the first isolation structure and second isolation structure each have a top width and a bottom width, wherein the bottom width is greater than the top width;
- and
- a device region of the semiconductor material layer disposed between the first isolation structure and the second isolation structure, wherein the device region has a device formed therein.
2 more elements
A device comprising:
- an insulating layer disposed over a substrate;
- a semiconductor layer disposed over the insulating layer;
- a first isolation structure and a second isolation structure embedded in the semiconductor layer, each of the first isolation structure and the second isolation structure extending into the insulating layer, each of the first isolation structure and the second isolation structure having angled sidewalls, wherein a first angle between an upper surface of the first isolation structure and a first adjoining sidewall of the first isolation structure is less than 90 degrees;
- and
- a device region disposed between the first isolation structure and the second isolation structure.
2 more elements
A device comprising:
- a film stack comprising an insulator layer disposed over a substrate and a semiconductor layer disposed over the insulator layer;
- a first set of isolation structures embedded in the film stack, the first set of isolation structures each having non-vertical sidewalls, an upper surface, and a bottom surface, wherein a first width of the upper surface is greater than a second width of the bottom surface;
- and
- a device region of the semiconductor layer laterally surrounded by the first set of isolation structures.
1 more element
Dependencies are inferred from the claim text.