Performing annealing process to improve fin quality of a finfet semiconductor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Po-Kang Ho
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Abstract
A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.
Claims20
A method of fabricating a semiconductor device, comprising:
- providing a semiconductor device having a fin structure that protrudes vertically upwards;
- reducing a lateral dimension of the fin structure;
- forming a semiconductor layer on the fin structure after the reducing of the lateral dimension;
- performing an annealing process to the semiconductor device after the forming of the semiconductor layer;
- and
- forming a dielectric layer over the fin structure after the performing of the annealing process.
A method of fabricating a semiconductor device, comprising:
- providing a semiconductor device having a fin structure that protrudes vertically upwards;
- performing a fin trimming process to reduce a lateral dimension of the fin structure, wherein the fin structure has roughened surfaces after the fin trimming process;
- forming a silicon cap layer on the fin structure after the fin trimming process has been performed;
- annealing the semiconductor device after the silicon cap layer has been formed, wherein the fin structure has less roughened surfaces after the annealing;
- and
- converting at least a portion of the silicon cap layer into a dielectric layer after the annealing.
A semiconductor device, comprising:
- a substrate that contains a semiconductive material;
- a fin structure that protrudes out of the substrate, wherein the fin structure is a fin structure for a p-type FinFET transistor;
- a silicon cap layer disposed on the fin structure;
- and
- a dielectric layer disposed on the silicon cap layer;
- wherein:
- the fin structure has a line width roughness (LWR) between about 1.7 nanometers (nm) and about 1.9 nm;
- and
- the fin structure has a line edge roughness (LER) between about 1.5 nanometers (nm) and about 1.7 nm.
Dependencies are inferred from the claim text.