Semiconductor memory device, operating method thereof, and memory system
AssigneeSK hynix Inc.
InventorJae Ho LEE
Life of this patent
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Abstract
A semiconductor memory device includes a switching controller, a voltage generator and control logic. The switching controller is connected to a local word line. The voltage generator, connected to the switching controller, is configured to generate an operating voltage according to an input clock signal and transfer the operating voltage to the switching controller. The control logic is configured to control operations of the voltage generator and the switching controller. The control logic is configured to detect an amount of leakage current of the local word line by counting a number of pulses of the input clock signal.
Claims20
A semiconductor memory device comprising:
- a switching controller connected to a local word line;
- a voltage generator, connected to the switching controller, configured to generate an operating voltage according to an input clock signal and transfer the operating voltage to the switching controller;
- and
- control logic configured to control operations of the voltage generator and the switching controller,
- wherein the control logic is configured to detect an amount of leakage current of the local word line by counting a number of pulses of the input clock signal.
A method for operating a semiconductor memory device, the method comprising:
- counting a number of pulses of a clock signal input to a charge pump during a measurement period based on a reference current (reference clock number);
- counting a number of pulses of the clock signal input to the charge pump during the measurement period based on a leakage current of a word line of a target memory block (target clock number);
- and
- determining whether the leakage current of the word line is larger than the reference current by comparing the reference clock number and the target clock number.
A method for operating a semiconductor memory device, the method comprising:
- counting a number of pulses of a clock signal input to a charge pump during a measurement period based on a first reference current (first reference clock number);
- counting a number of pulses of the clock signal input to the charge pump during the measurement period based on a second reference current different from the first reference current (second reference clock number);
- calculating a third reference clock number corresponding to a third reference current based on the first reference clock number and the second reference clock number;
- counting a number of pulses of the clock signal input to the charge pump during the measurement period based on a leakage current of a local word line of a target memory block (target clock number);
- and
- determining whether current has been leaked through the target memory block by comparing the third reference clock number with the target clock number.
A memory system comprising:
- a plurality of semiconductor memory devices;
- a power manager configured to manage power transferred to the plurality of semiconductor memory devices;
- and
- a memory controller configured to control operations of the plurality of semiconductor memory devices and the power manager,
- wherein each of the plurality of semiconductor memory devices includes:
- a memory cell array including a plurality of memory blocks;
- and
- a leakage current detector configured to detect a leakage current of each of the plurality of memory blocks.
Dependencies are inferred from the claim text.