Monitoring and charging inhibit bit-line
AssigneeMicron Technology, Inc.
InventorShigekazu Yamada
Life of this patent
Estimating the term…
Abstract
Discussed herein are systems and methods for charging a bit line (BL) during programming of non-volatile memory cells. An embodiment of a memory device comprises a group of memory cells including a first memory cell coupled to a first BL and a second memory cell coupled to a second BL, and a BL charging circuit that provides an inhibit signal to the second BL in response to a control signal to program the first memory cell. To provide the inhibit signal, the BL charging circuit apply a supply voltage to the second BL for an initial wait time and, after the initial wait time, apply a higher voltage than the supply voltage, until the inhibit signal reaches a value of the supply voltage. The first memory cells is programmed in response to the established voltage on the second BL.
Claims20
A memory device, comprising:
- a group of memory cells including a first memory cell coupled to a first bit line (BL) and a second memory cell coupled to a second BL;
- and
- a BL charging circuit configured to provide an inhibit signal to the second BL in response to a control signal to program the first memory cell, wherein, to provide the inhibit signal, the BL charging circuit is configured to apply a supply voltage (VCC) to the second BL for an initial wait time and, after the initial wait time, to apply a higher voltage than the supply voltage (VCC) until the inhibit signal reaches a value of the supply voltage (VCC).
A memory device, comprising:
- an NAND memory cell array;
- a memory control circuit coupled to the NAND memory cell array via a group of bit lines (BLs), including a first BL coupled to a string of NAND memory cells including a target memory cell to be programmed by a programming operation, and a second BL coupled to a string of NAND memory cells including a non-target memory cell to not be programmed by the programming operation, wherein the memory control circuit is configured to, in response to a control signal to program the first memory cell:
- provide an inhibit signal to the second BL, wherein, to provide the inhibit signal, the memory control circuit is configured to apply a supply voltage (VCC) to the second BL for an initial wait time and, after the initial wait time, apply a higher voltage than the supply voltage (VCC) until the inhibit signal reaches a value of the supply voltage (VCC);
- and
- provide a programming signal to a word line (WL) coupled to the first memory cell when the inhibit signal on the second BL reaches a value of the supply voltage (VCC).
A method of programming a memory device that includes a group of memory cells including a first memory cell coupled to a first bit line (BL) and a second memory cell coupled to a second BL, the method comprising:
- in response to a control signal to program the first memory cell, providing an inhibit signal to the second BL by coupling a supply voltage (VCC) to the second BL for an initial wait time;
- and
- after the initial wait time, applying a higher voltage than the supply voltage (VCC) to the second BL until the inhibit signal reaches a value of the supply voltage (VCC).
Dependencies are inferred from the claim text.