Concurrent programming of multiple cells for non-volatile memory devices

An apparatus comprising:

• a set of non-volatile storage cells arranged into a first erase block and a second erase block, each erase block electrically connected to a set of bit lines, the first erase block comprising a first word line and the second erase block comprising a second word line;
• and
• a selection circuit configured to electrically select a first set of storage cells in the first erase block and a second set of storage cells in the second erase block;
• and
• a programming circuit configured to apply a programming pulse in a single pulse to the first word line and second word line to concurrently write the same data values to the first set of storage cells and to the second set of storage cells.

A system comprising:

• a set of non-volatile storage cells arranged into a NAND string, the NAND string connectable to a bit line and comprising a word line for each storage cell;
• and
• a controller configured to concurrently write data to two storage cells in the NAND string by:
• electrically selecting the bit line by setting a select gate transistor;
• electrically connecting a first word line corresponding to a first storage cell of the NAND string with a second word line corresponding to a second storage cell of the NAND string;
• and
• concurrently applying a programming pulse to the connected word lines to concurrently write the data to the first storage cell and the second storage cell.

A method comprising:

• electrically selecting a bit line for an array of non-volatile storage cells arranged into two blocks, the bit line connectable to storage cells in each of the two blocks;
• electrically connecting separate word lines in each of the two blocks that correspond to the storage cells in the two blocks;
• and
• concurrently applying a programming pulse to the connected word lines to concurrently program the storage cells in the two blocks.

An apparatus comprising:

• means for electrically selecting a bit line for storage cells in a set of non-volatile storage cells that are arranged into two blocks, the bit line optionally connected to a first string of storage cells in a first of the two blocks and a second string of storage cells in a second of the two blocks, the first string and the second string each comprising a set of word lines;
• means for electrically connecting a first word line included in the first string and a second word line included in the second string, the first word line and the second word line corresponding to a first storage cell included in the first string and a second storage cell included in the second string;
• and
• means for applying a single programming pulse, at an elevated voltage, to the connected word lines to concurrently program the first storage cell in the first string and the second storage cell in the second string.