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US 2020/0005869 A1Published application
Architecture for 3-d nand memory
AssigneeMicron Technology, Inc.
InventorsMidori Morooka, Tomoharu Tanaka
Life of this patent
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Abstract
Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.
Claims20
An apparatus, comprising:
- multiple stacked memory arrays, including a first array of memory cell strings and a second array of memory cell strings stacked over the first array, each memory cell string extending vertically, and including multiple memory cells;
- and
- a data plate associated with the first array and the second array, the data plate being located between the first array and the second array, and the date plate being shared by memory cell strings of the first array and the second array,
- wherein the first and second memory arrays are configured in multiple blocks, and wherein the multiple blocks each includes a memory cell string from the first array and a memory cell string from the second array.
1 more element
An apparatus, comprising:
- multiple stacked memory arrays, including a first array of vertical memory cell strings and a second array of vertical memory cell strings over the first array;
- and
- a data plate associated with the first array and the second array, the data plate being located between the first array and the second array, and the data plate being shared by memory cell strings of the first array and the second array.
A method, comprising:
- selecting a first vertical memory cell string in a first array including multiple vertical memory cell strings, the first array stacked over a second array including multiple vertical memory cell strings, the first array being disposed over the second array, wherein a shared data plate is located between the first array and the second array;
- detecting a first data state of a memory cell within the first vertical memory cell string at a shared data detector;
- selecting a second vertical memory cell string in the second array;
- and
- detecting a second data state of a vertical memory cell within the second vertical memory cell string at the shared data detector,
- wherein a block in a respective row of blocks includes the first vertical memory cell string from the first array and the second vertical memory cell string from the second array.
3 more elements
Dependencies are inferred from the claim text.