Memory circuit and method of operating same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJui-Che TSAI, Cheng Hung LEE, Shih-Lien Linus LU
Life of this patent
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Abstract
A memory circuit includes a first memory cell, a second memory cell, a pre-charge circuit and a sense amplifier. The pre-charge circuit is coupled to a first bit line and a second bit line. The pre-charge circuit is configured to charge the first bit line and the second bit line to a pre-charge voltage level responsive to a first signal. The sense amplifier is coupled to the first memory cell by the first bit line, and coupled to the second memory cell by the second bit line. The sense amplifier is responsive to a second signal and a third signal. The second signal and the third signal being different from the first signal.
Claims20
A memory circuit comprising:
- a first memory cell coupled to a first bit line;
- a second memory cell coupled to a second bit line;
- a pre-charge circuit coupled to the first bit line and the second bit line, the pre-charge circuit configured to charge the first bit line and the second bit line to a pre-charge voltage level responsive to a first signal;
- and
- a sense amplifier coupled to the first memory cell by the first bit line, and coupled to the second memory cell by the second bit line, the sense amplifier being responsive to a second signal and a third signal, the second signal and the third signal being different from the first signal, the sense amplifier comprising:
- a header switch coupled to a first supply voltage, and configured to provide the first supply voltage to the sense amplifier responsive to the second signal.
A memory circuit comprising:
- a word line;
- a first bit line;
- a second bit line;
- a memory array having a first memory cell and a second memory cell arranged in a first row, the first memory cell and the second memory cell being coupled to the word line;
- and
- an input output circuit comprising:
- a pre-charge circuit coupled to the first bit line and the second bit line, the pre-charge circuit configured to charge the first bit line and the second bit line to a pre-charge voltage level responsive to a first signal;
- and
- a sense amplifier coupled to the first memory cell by the first bit line, and coupled to the second memory cell by the second bit line, the sense amplifier being responsive to a first sense amplifier signal and a second sense amplifier signal different from the first sense amplifier signal.
A method, the method comprising:
- writing data to a first memory cell and a second memory cell:
- reading the data from the first memory cell and the second memory cell, wherein reading the data comprises:
- pre-charging, by a pre-charge circuit, a first bit line and a second bit line to a pre-charge voltage level based on a first signal, the pre-charge circuit being coupled to the first bit line and the second bit line;
- turning on a sense amplifier responsive to a second signal and a third signal, the second signal and the third signal being different from the first signal;
- and
- comparing a first voltage level of the first bit line with a second voltage level of the second bit line;
- and
- outputting a set of data based on the data stored in the first memory cell and the second memory cell that are reflected on the first bit line and the second bit line, respectively.
Dependencies are inferred from the claim text.