Gate driving circuit, dispaly apparatus and driving method thereof

A method of driving a display apparatus, the display apparatus comprising a display panel and a gate driving circuit,

• the display panel comprising a plurality of rows of gate lines sequentially arranged;
• the gate driving circuit comprising:
• a plurality of shift registers, the plurality of shift registers comprising a first group of shift registers and a second group of shift registers, the first group of shift registers being configured to provide scanning signals for odd-numbered rows of gate lines of the plurality of rows of gate lines in the display panel, and the second group of shift registers being configured to provide scanning signals for even-numbered rows of gate lines of the plurality of rows of gate lines in the display panel,
• the first group of shift registers comprising a plurality of first subgroups of shift registers, each of which comprises n shift registers, an output terminal of an A-th stage of shift register electrically coupled to an A-th row of gate line being electrically coupled to an input terminal of a (A+n)-th stage of shift register electrically coupled to a (A+n)-th row of gate line, where A is an odd number equal to or larger than 1, and n is greater than 2;
• the second group of shift registers comprising a plurality of second subgroups of shift registers, each of which comprises n shift registers, an output terminal of a (A+1)-th stage of shift register electrically coupled to a (A+1)-th row of gate line being electrically coupled to an input terminal of a (A+1+n)-th stage of shift register electrically coupled to a (A+1+n)-th row of gate line;
• a reset terminal of the A-th stage of shift register being electrically coupled to an output terminal of a (A+a+n)-th stage of shift register electrically coupled to a (A+a+n)-th row of gate line, and a reset terminal of the (A+1)-th stage of shift register being electrically coupled to an output terminal of a (A+a+n+1)-th stage of shift register electrically coupled to a (A+a+n+1)-th row of gate line, where a is a natural number smaller than n/2;
• wherein the method comprises:
• supplying a plurality of first initial control signals to first ones of shift registers in the first subgroups of shift registers sequentially according to sequential order of stage numbers of the first ones of shift registers in the first subgroups of shift registers;
• supplying a plurality of second initial control signals to first ones of shift registers in the second subgroups of shift registers sequentially according to sequential order of stage numbers of the first ones of shift registers in the second subgroups of shift registers;
• supplying first clock signals to shift registers in the first group of shift registers sequentially according to sequential order of stage numbers of the shift registers in the first group of shift registers;
• and
• supplying second clock signals to shift registers in the second group of shift registers sequentially according to sequential order of stage numbers of the shift registers in the second group of shift registers.