Display apparatus and inter-chip bus thereof
AssigneeRaydium Semiconductor Corporation
InventorsSHANG-HAN YU, SUNG-BO CHEN, CHIH-CHUAN HUANG
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Abstract
A display apparatus is disclosed. The display apparatus includes a display panel, a master timing controller embedded driver (TED), N slave TEDs and an inter-chip bus. N is a positive integer. The display panel has (N+1) display areas. The master TED is disposed corresponding to a first display area. The N slave TEDs are disposed corresponding to a second display area˜a (N+1)-th display area respectively and controlled by the master TED. The inter-chip bus includes a first wire and a second wire coupled between the master TED and N slave TEDs respectively and used for bi-directionally transmitting clock signal and data signal respectively.
Claims24
A display apparatus, comprising:
- a display panel having (N+1) display areas, wherein N is a positive integer;
- a master timing controller embedded driver, disposed corresponding to a first display area of the (N+1) display areas;
- N slave timing controller embedded drivers, disposed corresponding to a second display area to a (N+1)-th display area of the (N+1) display areas respectively and controlled by the master timing controller embedded driver;
- and
- an inter-chip bus, comprising:
- a first wire, coupled between the master timing controller embedded driver and the N slave timing controller embedded drivers, for bi-directionally transmitting a clock signal;
- and
- a second wire, coupled between the master timing controller embedded driver and the N slave timing controller embedded drivers, for bi-directionally transmitting a data signal.
An inter-chip bus, applied to a display apparatus comprising a display panel, a master timing controller embedded driver and N slave timing controller embedded drivers, the display panel having (N+1) display areas, N being a positive integer, the master timing controller embedded driver being disposed corresponding to a first display area of the (N+1) display areas, the N slave timing controller embedded drivers being disposed corresponding to a second display area to a (N+1)-th display area of the (N+1) display areas respectively and controlled by the master timing controller embedded driver, the inter-chip bus comprising:
- a first wire, coupled between the master timing controller embedded driver and the N slave timing controller embedded drivers, for bi-directionally transmitting a clock signal;
- and
- a second wire, coupled between the master timing controller embedded driver and the N slave timing controller embedded drivers, for bi-directionally transmitting a data signal.
Dependencies are inferred from the claim text.