Scheduler and simulator for a area-efficient, reconfigurable, energy-efficient, speed-efficient neural network substrate
AssigneeInternational Business Machines Corporation
InventorsPallab Datta, Dharmendra S. Modha
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Abstract
Mapping of logical neural cores to physical neural cores is provided. In various embodiments, a neural network description describing a plurality of logical cores is read. A plurality of precedence relationships is determined among the plurality of logical cores. Based on the plurality of precedence relationships, a directed acyclic graph among the plurality of logical cores is generated. By breadth first search of the directed acyclic graph, a schedule is generated. The schedule maps each of the plurality of logical cores to one of a plurality of physical cores at one of a plurality of time slices. Execution of the schedule is simulated.
Claims20
A method comprising:
- reading a neural network description describing a plurality of logical cores;
- determining a plurality of precedence relationships among the plurality of logical cores;
- based on the plurality of precedence relationships, generating a directed acyclic graph among the plurality of logical cores;
- by breadth first search of the directed acyclic graph, generating a schedule, the schedule mapping each of the plurality of logical cores to one of a plurality of physical cores at one of a plurality of time slices.
A computer program product for mapping logical neural cores to physical neural cores, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
- reading a neural network description describing a plurality of logical cores;
- determining a plurality of precedence relationships among the plurality of logical cores;
- based on the plurality of precedence relationships, generating a directed acyclic graph among the plurality of logical cores;
- by breadth first search of the directed acyclic graph, generating a schedule, the schedule mapping each of the plurality of logical cores to one of a plurality of physical cores at one of a plurality of time slices.
A system comprising:
- a plurality of physical neural cores;
- a computing node comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor of the computing node to cause the processor to perform a method comprising:
- reading a neural network description describing a plurality of logical cores;
- determining a plurality of precedence relationships among the plurality of logical cores;
- based on the plurality of precedence relationships, generating a directed acyclic graph among the plurality of logical cores;
- by breadth first search of the directed acyclic graph, generating a schedule, the schedule mapping each of the plurality of logical cores to one of the plurality of physical cores at one of a plurality of time slices;
- providing the schedule to the plurality of physical neural cores for execution.
The system 15, wherein each of the plurality of logical cores comprises a crossbar template, the crossbar template comprising synaptic weights for the logical core.
Dependencies are inferred from the claim text.