Neural network circuit device, neural network, neural network processing method, and neural network execution program
AssigneeTokyo Institute of Technology
InventorsHiroki NAKAHARA, Haruyoshi YONEKAWA
Life of this patent
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Abstract
A binarized neural network circuit includes: an input part configured to allow input of input values (binary) and weights; an XNOR gate circuit configured to receive the input values and the weights and take XNOR logic; a multibit bias input part configured to allow input of a multibit bias; a sum circuit part configured to sum each of XNOR logical values and the multibit bias; and an activation circuit part configured to output only a sign bit of a multibit signal generated by using the sum.
Claims22
A neural network circuit device which is provided in a neural network including at least an input layer, one or more intermediate layers, and an output layer, and in which an input value is multiplied by a weight and a bias in the intermediate layer, the neural network circuit device comprising:
- a logic circuit part configured to receive an input value xi and a weight wi and perform a logical operation;
- a sum circuit part configured to receive a multibit bias W′ and sum an output from the logic circuit part and the multibit bias W′;
- and
- an activation circuit part configured to output only a sign bit of a multibit signal Y generated by using the sum.
A neural network processing method which is provided in a neural network including at least an input layer, one or more intermediate layers, and an output layer, and in which an input value is multiplied by a weight and a bias in the intermediate layer, the neural network processing method comprising the steps of:
- receiving an input value xi and a weight wi and performing a logical operation;
- receiving a multibit bias W′ and summing an output from the logic circuit part and the multibit bias W′;
- and
- outputting only a sign bit of a multibit signal Y generated by using the sum.
A neural network execution program embodied on a non-transitory computer-readable medium, the program for causing a computer serving as a neural network circuit device which is provided in a neural network including at least an input layer, one or more intermediate layers, and an output layer, and in which an input value is multiplied by a weight and a bias in the intermediate layer,
- wherein the neural network circuit device comprises:
- a logic circuit unit configured to receive an input value xi and a weight wi and perform a logical operation;
- a sum circuit unit configured to receive a multibit bias W′ and sum an output from the logic circuit part and the multibit bias W′;
- and
- an activation circuit unit configured to output only a sign bit of a multibit signal Y generated by using the sum.
Dependencies are inferred from the claim text.