Security Monitoring of SPI Flash
AssigneeNuvoton Technology Corporation
InventorsZiv Hershman, Yoel Hayon, Natan Keren, Moshe Alon
Life of this patent
Estimating the term…
Abstract
A security device includes an interface and a processor. The interface is configured for connecting to a bus that serves one or more peripheral devices, at least one of the peripheral devices being a memory device. The processor is connected to the bus in addition to the peripheral devices, and is configured to hold a definition that distinguishes between authorized and unauthorized transactions with the memory device, to identify on the bus a transaction in which a bus-master device attempts to access the memory device, and to initiate a responsive action in response to identifying that the transaction is unauthorized in accordance with the definition.
Claims33
A security device, comprising:
- an interface for connecting to a bus that serves one or more peripheral devices, at least one of the peripheral devices being a memory device;
- and
- a processor, which is connected to the bus in addition to the peripheral devices, and which is configured to hold a definition that distinguishes between authorized and unauthorized transactions with the memory device, to identify on the bus a transaction in which a bus-master device attempts to access the memory device, and to initiate a responsive action in response to identifying that the transaction is unauthorized in accordance with the definition.
The security device according to claim wherein the bus comprises (i) one or more dedicated signals that are each dedicated to a respective one of the peripheral devices, and (ii) one or more shared signals that are shared among the peripheral devices served by the bus, and wherein the processor is configured to disrupt the transaction on the bus by disrupting a dedicated signal associated with the memory device.
The security device according to claim wherein the transaction is a write transaction in which the bus-master device writes data to the memory device, and wherein the processor is configured to perform a cryptographic operation on the data, and to decide that the transaction is authorized in response to a success of the cryptographic operation.
A security device, comprising:
- an interface for connecting to a bus that serves one or more peripheral devices, at least one of the peripheral devices being a memory device;
- and
- a processor, which is connected to the bus in addition to the peripheral devices and is configured to identify on the bus a transaction in which a bus-master device attempts to access the memory device, to initiate a responsive action upon identifying the transaction, and to respond to the bus-master device instead of the given peripheral device.
A security method, comprising:
- communicating over a bus using a security device, which is connected to the bus in addition to one or more peripheral devices, at least one of the peripheral devices being a memory device;
- holding in the security device a definition that distinguishes between authorized and unauthorized transactions with the memory device;
- and
- using the security device, identifying on the bus a transaction in which a bus-master device attempts to access the memory device, and initiating a responsive action in response to identifying that the transaction is unauthorized in accordance with the definition.
A security method, comprising:
- communicating over a bus using a security device, which is connected to the bus in addition to one or more peripheral devices, at least one of the peripheral devices being a memory device;
- and
- using the security device, identifying on the bus a transaction in which a bus-master device attempts to access the memory device, initiating a responsive action upon identifying the transaction, and responding to the bus-master device instead of the given peripheral device
Dependencies are inferred from the claim text.