US 2020/0004703 A1 · NON-POSTED WRITE TRANSACTIONS

Abstract

Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

Claims25

Dependent claims

An apparatus comprising:

a controller;
and
a command queue to buffer incoming write requests into the apparatus;
the controller to:
receive, from a client across a link, a non-posted write request in a transaction layer packet (TLP) to the command queue;
determine that the command queue can accept the non-posted write request;
generate a completion message;
set a bit in a completion status field of the completion message to a value that indicates a successful completion (SC) that indicates that the non-posted write request was accepted into the command queue;
and
transmit, to the client across the link, the completion message with the SC that indicates that the non-posted write request was accepted into the command queue.

7 more elements

Dependencies are inferred from the claim text.

Non-posted write transactions

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Non-posted write transactions

Life of this patent

Abstract

Claims25