Variable-stride write in a multi-point bus architecture

An apparatus for data communication comprising:

• a plurality of registers;
• an interface circuit adapted to couple the apparatus to a serial bus;
• and
• a processor configured to:
• cause a first data byte received in a first field of a datagram received from the serial bus to be written to a first register, wherein the first register is located at an address indicated by an address pointer;
• cause the address pointer to be modified by addition or subtraction of a stride value provided in a second field of the datagram to obtain a modified address pointer;
• and
• cause a second data byte received in a third field of the datagram to be written to a second register in the apparatus, wherein the second register is located at an address indicated by the modified address pointer, and wherein the first register and the second register are located at non-contiguous addresses.

A processor-readable storage medium comprising code for:

• writing a first data byte received in a first field of a datagram from a serial bus to a first register in a slave device, wherein the first register is located at an address indicated by an address pointer;
• modifying the address pointer by adding or subtracting a stride value provided in a second field of the datagram to obtain a modified address pointer;
• and
• writing a second data byte received in a third field of the datagram to a second register in the slave device, wherein the second register is located at an address indicated by the modified address pointer, and wherein the first register and the second register are located at non-contiguous addresses.