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US 2020/0004689 A1Published application
Memory constrained translation table management
AssigneeMicron Technology, Inc.
InventorSebastien Andre Jean
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AssigneeMicron Technology, Inc.
InventorSebastien Andre Jean
Estimating the term…
Devices and techniques for memory constrained translation table management are disclosed herein. A level of a translation table is logically segmented into multiple segments. Here, a bottom level of the translation table includes a logical to physical address pairing for a portion of a storage device and other levels of the translation table include references within the translation table. The multiple segments are written to the storage device. A first segment of the multiple segments is loaded to byte-addressable memory. A request for an address translation is received and determined to be for an address referred to by a second segment of the multiple segments. The first segment is then replaced with the second segment in the byte-addressable memory and the request is fulfilled using the second segment to locate a lower level of the translation table that includes the address translation.
A device for memory translation table management, the device comprising:
A method for memory translation table management, the method comprising:
A machine-readable medium including instructions for memory translation table management, the instructions, when executed by processing circuitry, cause the processing circuitry to perform operations comprising:
Dependencies are inferred from the claim text.