Back to results
US 2020/0004683 A1Published application
Cache partitioning mechanism
AssigneeIntel Corporation
InventorsNicolas Kacevas, Niranjan Cooray, Parth Damani, Pritav Shah
Life of this patent
Estimating the term…
Abstract
An apparatus to facilitate cache partitioning is disclosed. The apparatus includes a set associative cache to receive access requests from a plurality of agents and partitioning logic to partition the set associative cache by assigning sub-components of a set address to each of the plurality of agents.
Claims25
An apparatus to facilitate cache partitioning, comprising:
- a set associative cache to receive access requests from a plurality of agents;
- and
- partitioning logic to partition the set associative cache by assigning sub-components of a set address to each of the plurality of agents.
A method to facilitate cache partitioning, comprising:
- receiving request from one a plurality of agents to access a set associative cache;
- and
- partitioning the set associative cache by assigning sub-components of a set address to each of the plurality of agents.
A system to facilitate cache partitioning, comprising:
- a memory;
- a memory management unit (MMU) coupled to the memory including a set associative cache translation lookaside buffer (TLB);
- and
- partitioning logic to partition the TLB by assigning sub-components of a set address to each of plurality of agents requesting access to the memory.
1 more element
Dependencies are inferred from the claim text.