Memory device including page buffers

A memory device comprising:

• a plurality of bit lines;
• and
• a page buffer circuit in which a plurality of page buffers electrically coupled to the plurality of bit lines are arranged in a matrix,
• wherein the plurality of page buffers are grouped into a plurality of page buffer input/output units in correspondence to a data input/output processing unit, and
• wherein page buffers of one page buffer input/output unit are disposed over at least two columns.

A memory device comprising:

• a plurality of bit lines;
• and
• a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines,
• wherein the page buffer circuit is divided into a first page buffer group and a second page buffer group depending on corresponding data input/output pins, and
• wherein each of the first page buffer group and the second page buffer group has an odd number of stages.

A memory device comprising:

• first and second arrays of page buffers coupled to bit lines;
• and
• first and second arrays of caches electrically coupled to the first and second arrays of page buffers, respectively, and electrically coupled to first and second data pin groups, respectively,
• wherein a row size of each array of page buffers is smaller than a row size of each array of caches.