Controlling nand operation latency
AssigneeMicron Technology, Inc.
InventorsGiuseppe D'Eliseo, Luigi Esposito, Xinghui Duan, Lucia Santojanni, Massimo Iaculo
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicron Technology, Inc.
InventorsGiuseppe D'Eliseo, Luigi Esposito, Xinghui Duan, Lucia Santojanni, Massimo Iaculo
Estimating the term…
Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.
A device for controlling NAND operation latency, the device comprising:
A method for controlling NAND operation latency, the method comprising:
A machine readable medium including instructions for controlling NAND operation latency, the instructions, when executed by processing circuitry of a machine, cause the processing circuitry to perform operations comprising:
Dependencies are inferred from the claim text.