Memory controlling device and memory system including the same

A memory controlling device connected to a memory subsystem including a first memory module and second memory module implemented by a phase-change memory and a third memory module implemented by a memory whose write speed is faster than that of the phase-change memory via a plurality of channels, the memory controlling device comprising:

• a memory controller that:
• divides original data stored in a buffer into a plurality of sub-data including first sub-data and second sub-data;
• generates a non-blocking code from the plurality of sub-data;
• writes the first sub-data to the first memory module, writes the second sub-data to the second memory module, and writes the non-blocking code to the third memory module, at migration;
• and
• reconstructs the original data from the first sub-data read from the first memory module and the non-blocking code read from the third memory module without reading the second sub-data from the second memory module, under a predetermined condition at a read request from the CPU,
• wherein a memory cell array of the second memory module is partitioned into a plurality of partitions, and
• wherein the predetermined condition includes a condition that a write operation is being performed in a partition in which the second sub-data are stored.

A memory system comprising:

• a memory subsystem including a first memory module and second memory module implemented by a phase-change memory and a third memory module implemented by a memory whose write speed is faster than that of the phase-change memory via a plurality of channels;
• and
• a memory controlling device connected to the memory subsystem and including a memory controller that:
• divides original data stored in a buffer into a plurality of sub-data including first sub-data and second sub-data;
• generates a non-blocking code from the plurality of sub-data;
• writes the first sub-data to the first memory module, writes the second sub-data to the second memory module, and writes the non-blocking code to the third memory module, at migration;
• and
• reconstructs the original data from the first sub-data read from the first memory module and the non-blocking code read from the third memory module without reading the second sub-data from the second memory module, under a predetermined condition at a read request from the CPU,
• wherein a memory cell array of the second memory module is partitioned into a plurality of partitions, and
• wherein the predetermined condition includes a condition that a write operation is being performed in a partition in which the second sub-data are stored.