Debug boundaries for hardware accelerators
AssigneeInternational Business Machines Corporation
InventorsPaul E. Schardt, Jim C. Chen, Lance G. Thompson, James E. Carey
Life of this patent
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Abstract
An accelerator tester partitions accelerator logic for a hardware accelerator into a plurality of sequential logic blocks, defines debug boundaries between adjacent sequential logic blocks, and inserts logic corresponding to the plurality of debug boundaries into the accelerator logic. The accelerator tester then tests the accelerator logic that includes the logic corresponding to the debug boundaries, and when the test fails, determines which of the debug boundaries were successfully crossed during the test. The information of which of the debug boundaries were successfully crossed during the test can then be fed back into a subsequent test by the accelerator tester.
Claims18
An apparatus comprising:
- at least one processor;
- a memory coupled to the at least one processor;
- and
- an accelerator tester residing in the memory and executed by the at least one processor, wherein the accelerator tester receives accelerator logic for a hardware accelerator, partitions the accelerator logic into a plurality of sequential logic blocks, defines a plurality of debug boundaries between at least two adjacent sequential logic blocks, and inserts logic corresponding to the plurality of debug boundaries into the accelerator logic.
A method for testing accelerator logic for a hardware accelerator, the method comprising:
- partitioning the accelerator logic into a plurality of sequential logic blocks;
- defining a plurality of debug boundaries between at least two adjacent sequential logic blocks;
- and
- inserting logic corresponding to the plurality of debug boundaries into the accelerator logic.
A method for testing accelerator logic for a hardware accelerator, the method comprising:
- partitioning the accelerator logic into a plurality of sequential logic blocks;
- defining a plurality of debug boundaries between at least two adjacent sequential logic blocks;
- inserting logic corresponding to the plurality of debug boundaries into the accelerator logic;
- testing the accelerator logic that includes the logic corresponding to the plurality of debug boundaries;
- when the test succeeds, reporting the test succeeded;
- when the test fails:
- determining which of the plurality of debug boundaries were successfully crossed during the test;
- determining from the plurality of debug boundaries successfully crossed during the test in which of the plurality of sequential logic blocks a failure occurred;
- and
- feeding back results of the test that indicate where the failure occurred to a subsequent test.
Dependencies are inferred from the claim text.