Apparatus and method for detecting and recovering from data fetch errors

An apparatus comprising:

• error-processing circuitry communicatively coupled to at least one of a plurality of instruction processing stages, the error-processing circuitry to detect an error associated with execution of a program by the plurality of instruction processing stages;
• and
• a machine-check global status (MCG_STATUS) register to store a plurality of global status fields including:
• a restart IP valid (RIPV) field to indicate whether execution of the program can be reliably restarted at an instruction referenced by an instruction pointer, the instruction pointer pushed onto a stack by a machine-check error mechanism;
• and
• an error IP valid (EIPV) field to indicate whether the instruction referenced by the instruction pointer is responsible for the detected error.

A computer system comprising:

• a central processing unit including at least one processor core, the at least one processor core comprising:
• error-processing circuitry in communicatively coupled to at least one of a plurality of instruction processing stages, the error-processing circuitry to detect an error associated with execution of a program by the plurality of instruction processing stages;
• and
• a machine-check global status (MCG_STATUS) register to store a plurality of global status fields including:
• a restart IP valid (RIPV) field to indicate whether execution of the program can be reliably restarted at an instruction referenced by an instruction pointer, the instruction pointer pushed onto a stack by a machine-check error mechanism;
• and
• an error IP valid (EIPV) field to indicate whether the instruction referenced by the instruction pointer is responsible for the detected error;
• and
• at least one input/output interface communicatively coupling the central processing unit to one or more input/output devices.

An apparatus comprising:

• error-processing circuitry communicatively coupled to at least one of a plurality of instruction processing stages, the error-processing circuitry to detect an error associated with execution of a program by the plurality of instruction processing stages;
• and
• a machine-check status (MCi_STATUS) register to store a plurality of status fields including:
• a machine-check architecture (MCA) error code field to store an error code associated with the detected error;
• an uncorrected (UC) field to store an indication of whether the detected error is an uncorrected error;
• a processor context corrupt (PCC) field to store an indication of whether a processor context or state is corrupt due to the detected error;
• an address valid (ADDRV) field to store an indication of whether a valid address is stored in a machine-check address (MCi_ADDR) register;
• and
• a miscellaneous valid (MISCV) field to store an indication of whether valid content is stored in a machine-check miscellaneous (MCi_MISC) register.