US 2020/0004602 A1 · SYSTEM, APPARATUS AND METHOD FOR BARRIER SYNCHRONIZATION IN A MULTI-THREADED PROCESSOR

Abstract

In one embodiment, a first processor core includes: a plurality of execution pipelines each to execute instructions of one or more threads; a plurality of pipeline barrier circuits coupled to the plurality of execution pipelines, each of the plurality of pipeline barrier circuits associated with one of the plurality of execution pipelines to maintain status information for a plurality of barrier groups, each of the plurality of barrier groups formed of at least two threads; and a core barrier circuit to control operation of the plurality of pipeline barrier circuits and to inform the plurality of pipeline barrier circuits when a first barrier has been reached by a first barrier group of the plurality of barrier groups. Other embodiments are described and claimed.

Claims20

Dependent claims

A processor comprising:

a first core comprising:
a plurality of execution pipelines each to execute instructions of one or more threads;
a plurality of pipeline barrier circuits coupled to the plurality of execution pipelines, each of the plurality of pipeline barrier circuits associated with one of the plurality of execution pipelines to maintain status information for a plurality of barrier groups, each of the plurality of barrier groups formed of at least two threads;
and
a core barrier circuit to control operation of the plurality of pipeline barrier circuits and to inform the plurality of pipeline barrier circuits when a first barrier has been reached by a first barrier group of the plurality of barrier groups.

2 more elements

At least one computer readable storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

receiving, in a core barrier circuit of a first core of a processor from a first pipeline barrier circuit of the first core, a barrier reach indication, the barrier reach indication to indicate that a first thread of a first barrier group having a plurality of threads has reached a first barrier;
updating, via the core barrier circuit, an active count for the first barrier group based on the barrier reach indication;
determining, in the core barrier circuit, whether the active count corresponds to a configured count for the first barrier group;
and
in response to determining that the active count corresponds to the configured count, informing the plurality of threads of the first barrier group that the first barrier has been reached by the plurality of threads.

2 more elements

Dependencies are inferred from the claim text.

System, apparatus and method for barrier synchronization in a multi-threaded processor

Life of this patent

System, apparatus and method for barrier synchronization in a multi-threaded processor

Life of this patent

Abstract

Claims20