Techniques for reducing serialization in divergent control flow

A compute unit comprising:

• a command processor;
• and
• a single instruction multiple data unit (“SIMD unit”) configured to execute a shader program having divergent control flow,
• wherein the command processor is configured to:
• detect entry of the shader program into a divergent section;
• in response to the detecting, store one or more task list entries into one or more task lists for one or more lanes executing the shader program;
• identify a plurality of task list entries of one of the one or more task lists;
• and
• schedule a plurality of work-items for execution as a wavefront based on the identified plurality of task list entries.

An accelerated processing device comprising:

• a plurality of compute units configured to execute shader programs, wherein at least one of the compute units is configured to execute a shader program having divergent control flow by:
• detecting entry of the shader program into a divergent section;
• in response to the detecting, storing one or more task list entries into one or more task lists for one or more lanes executing the shader program;
• identifying a plurality of task list entries of one of the one or more task lists;
• and
• scheduling a plurality of work-items for execution as a wavefront based on the identified plurality of task list entries.