Memory access optimization in a processor complex

A system for memory access optimization in a processor complex comprising:

• a plurality of logical partitions comprising a first host and a second host distributed between one or more processors of one or more processing nodes in one or more drawers of the processor complex, wherein the first host is configured to:
• determine one or more offload criteria for offloading a memory movement process in the processor complex;
• identify a memory movement process parameter corresponding to the one or more offload criteria;
• determine a processor location of the first host;
• exchange a plurality of memory credentials with the second host;
• determine a distance from the processor location of the first host to the second block location based on the memory credentials, wherein the distance identifies whether the first host and the second host are located on a same or a different one of the one or more drawers and the one or more processing nodes;
• schedule movement of a block of memory from a first block location at the first host to a second block location at the second host as the memory movement process performed by an offload engine based on determining that the memory movement process parameter exceeds at least one of the offload criteria, wherein the at least one of the offload criteria comprises an offload minimum memory block size, and the memory movement process parameter comprises a block size of the block of memory;
• determine the offload minimum memory block size as at least one of the offload criteria based on the distance from the processor location of the first host to the second block location;
• and
• move the block of memory from the first block location at the first host to the second block location at the second host as the memory movement process performed by the first host based on determining that the memory movement process parameter does not exceed the at least one of the offload criteria.

A computer program product for memory access optimization in a processor complex, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processing circuitry to cause the processing circuitry to perform:

• determining one or more offload criteria for offloading a memory movement process in the processor complex;
• identifying a memory movement process parameter corresponding to the one or more offload criteria;
• determining a processor location of a first host;
• exchanging a plurality of memory credentials with a second host;
• determining a distance from the processor location of the first host to the second block location based on the memory credentials;
• scheduling movement of a block of memory from a first block location at the first host to a second block location at the second host as the memory movement process performed by an offload engine based on determining that the memory movement process parameter exceeds at least one of the offload criteria, wherein the at least one of the offload criteria comprises an offload minimum memory block size, and the memory movement process parameter comprises a block size of the block of memory;
• determining the offload minimum memory block size as at least one of the offload criteria based on the distance from the processor location of the first host to the second block location;
• and
• moving the block of memory from the first block location at the first host to the second block location at the second host as the memory movement process performed by the first host based on determining that the memory movement process parameter does not exceed the at least one of the offload criteria.