Reconfigurable Parallel Processing
AssigneeAzurEngine Technologies Zhuhai Inc.
InventorsYuan Li, Jianbin Zhu
Life of this patent
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Abstract
Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.
Claims22
1-38. (canceled)
A processor, comprising
- a plurality of processing elements (PEs);
- a plurality of switch boxes arranged in a plurality of columns, each of the plurality of switch boxes being associated with a respective PE and configured to provide input data switching for the respective PE;
- a plurality of memory ports arranged in the plurality of columns and being coupled to a memory unit and a top switch box in each column of the plurality of columns, each of the plurality of memory port being configured to provide data access to the memory unit for one or more switch boxes in a respective column;
- a plurality of inter-column switch boxes (ICSBs) each coupled to a bottom switch box in each column of the plurality of columns;
- and
- a gasket memory with its input coupled to a memory port, a PE, one or more switch boxes and an ICSB in a last column of the plurality of columns, and its output coupled to a memory port, one or more switch boxes and an ICSB in a first column of the plurality of columns.
A processor, comprising:
- a plurality of processing elements (PEs) each comprising a configuration buffer and a plurality of arithmetic logic units (ALUs), and each configured to operate independently according to respective PE configurations stored in the configuration buffer;
- and
- a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.
56-210. (canceled)
A method, comprising:
- executing a first instruction at a reconfigurable processing element a number of times according to a first configuration, the reconfigurable processing element being configured to be part of a first physical data path during the first configuration;
- delivering an execution result from the reconfigurable processing element to a gasket memory to temporality store the execution result after each execution of the first instruction;
- and
- feeding the execution result stored in the gasket memory to a second physical data path.
Dependencies are inferred from the claim text.