US 2020/0004552 A1 · PROCESSOR INSTRUCTION SUPPORT TO DEFEAT SIDE-CHANNEL ATTACKS

Abstract

Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.

Claims20

Dependent claims

An apparatus comprising:

a decoder to decode a first instruction, the first instruction having at least a first field for a first opcode to indicate that execution circuitry is to set a first flag in a first register to indicate a mode of operation that is to cause a redirection of program flow to an exception handler upon the occurrence of an event;
and
execution circuitry to execute the decoded first instruction to set the first flag in the first register to indicate the mode of operation and to store an address of an exception handler in a second register.

Dependencies are inferred from the claim text.

Facts

Application

16/024,733Filed 29 Jun 2018

Published

2 Jan 2020

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 9/3865
Recovery, e.g. branch miss-prediction, exception handling: using deferred exception handling, e.g. exception flags
G06F 12/1491
By checking the subject access rights: in a hierarchical protection system, e.g. privilege levels, memory rings
G06F 9/30134
Organisation of register space, e.g. banked or distributed register file: register stacks; shift registers
G06F 9/3016
Instruction analysis, e.g. decoding, instruction word fields: decoding the operand specifier, e.g. specifier format

Processor instruction support to defeat side-channel attacks

Life of this patent

Processor instruction support to defeat side-channel attacks

Life of this patent

Abstract

Claims20