Branch target buffer for a data processing apparatus

A data processing method comprising:

• predicting an outcome of a branch instruction;
• storing in a branch target buffer, BTB, a plurality of BTB entries, each BTB entry comprising both a branch indexing address and a predicted branch target address for a branch instruction, the branch indexing address to map to a program counter of an instruction being fetched wherein a BTB hit returns a predicted branch target address corresponding to the program counter;
• storing in one of a plurality of storage slots of a fetch target queue, at least one instruction address predicted using the branch prediction circuitry, the storage slots queueing instructions to be fetched for execution;
• fetching and returning from a memory, for execution by a processor, instructions corresponding to instruction addresses taken from a top of the fetch target queue;
• and
• reading an entry from the fetch target queue other than the top entry and sending a prefetch probe to the memory to determine if a corresponding instruction is stored in an instruction cache of the memory;
• and
• triggering issuance of a BTB miss probe to the memory, in response to detection by the BTB of a BTB miss for the program counter when populating the fetch target queue, the BTB miss probe to initiate fetching at least one instruction from the memory to resolve the BTB miss.

Machine-readable instructions provided on a storage medium or on a transmission medium, the instructions upon execution by one or more processors to cause the processor(s) to:

• predict an outcome of a branch instruction;
• store in a branch target buffer, BTB, a plurality of BTB entries, each BTB entry comprising both a branch indexing address and a predicted branch target address for a branch instruction, the branch indexing address to map to a program counter of an instruction being fetched wherein a BTB hit returns a predicted branch target address corresponding to the program counter;
• store in one of a plurality of storage slots of a fetch target queue, at least one instruction address predicted as a branch target using the branch prediction circuitry, the storage slots queueing instructions to be fetched for execution;
• fetch and return from a memory for execution, instructions corresponding to an instruction address taken from a top of the fetch target queue;
• and
• read an entry from the fetch target queue other than the top entry and send a prefetch probe to the memory to determine if at least one corresponding instruction is stored in an instruction cache of the memory;
• and
• trigger issuance of a BTB miss probe to the memory, in response to detection by the BTB of a BTB miss for the program counter when populating the fetch target queue, the BTB miss probe to initiate fetching of at least one instruction from the memory to resolve the BTB miss.