Accelerator apparatus and method for decoding and de-serializing bit-packed data

A method comprising:

• decoding a multiple load instruction to generate a decoded multiple load instruction comprising a plurality of operations, the multiple load instruction including an opcode, source operands, and at least one destination operand;
• storing N packed index values in a first source register;
• storing a base address value in a second source register;
• executing the operations of the decoded multiple load instruction, the operations including:
• combining the base address from the second source register with each of the N packed index values to generate N system memory addresses;
• retrieving N sets of data elements from the N system memory addresses;
• and
• storing the N sets of data elements in N vector destination registers identified by the at least one destination operand.

A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:

• decoding a multiple load instruction to generate a decoded multiple load instruction comprising a plurality of operations, the multiple load instruction including an opcode, source operands, and at least one destination operand;
• storing N packed index values in a first source register;
• storing a base address value in a second source register;
• executing the operations of the decoded multiple load instruction, the operations including:
• combining the base address from the second source register with each of the N packed index values to generate N system memory addresses;
• retrieving N sets of data elements from the N system memory addresses;
• and
• storing the N sets of data elements in N vector destination registers identified by the at least one destination operand.

A processor comprising:

• a decoder to decode a multiple store instruction to generate a decoded multiple store instruction comprising a plurality of operations, the multiple store instruction including an opcode and source operands;
• a first source register to store N packed index values;
• a second source register to store a base address value;
• execution circuitry to execute the operations of the decoded multiple store instruction, the execution circuitry comprising:
• parallel address generation circuitry to combine the base address from the second source register with each of the N packed index values to generate N system memory addresses;
• data store circuitry to copy the N sets of data elements from N vector source registers to the N system memory addresses.