Register bank conflict reduction for multi-threaded processor

A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:

• receiving a plurality of SIMD (Single Instruction Multiple Data) instructions for processing for an execution unit (EU) in a processing system, the EU including a register file with a plurality of arrays of register banks, the plurality of arrays of register banks including a first array of register banks for even registers and a second array of register banks for odd registers, and including a processing pipeline, the processing pipeline including a plurality of stages for reading registers;
• analyzing source operands of the plurality of SIMD instructions to identify whether one or more register bank conflicts will occur if source operands of one or more instructions are read in a same clock cycle;
• and
• upon determining that one or more register bank conflicts will occur, swapping positions of source operands within one or more of the plurality of SIMD instructions to avoid the one or more register bank conflicts.

A processing system comprising:

• one or more graphical processing units (GPUs), at least one of the one or more GPUs including a plurality of execution units (EUs), the plurality of EUs including at least a first EU to process a plurality of threads, wherein processing a thread includes processing SIMD (Single Instruction Multiple Data) instructions, wherein the first EU includes:
• a register file with a plurality of arrays of register banks, each of the plurality of arrays including a plurality of register banks with each register bank including a plurality of registers, the plurality of arrays of register banks including first array of register banks for even registers and a second array of register banks for odd registers, and
• a first read multiplexer to read registers from the first array of register banks and a second read multiplexer to read registers from the second array of register banks, wherein attempting to read more than one register from a single register bank of the register file in a same clock cycle generates a register bank conflict;
• and
• memory to store data for graphics processing;
• wherein registers for each thread for the first EU are distributed across the register banks of the register file such that a first register for a thread and a following second register for the thread within an array of register banks are located in different register banks and wherein the registers for each thread are distributed such that all even registers are located in the first array of register banks and all odd registers are located in the second array of register banks.