High performance expression evaluator unit
AssigneeMicrosoft Technology Licensing, LLC
InventorCharles Neill Boyd
Life of this patent
Estimating the term…
Abstract
Devices and methods for limiting register usage through the use of fixed function processing is provided. The method may include receiving instructions executable by a processor. The method may also include that a set of the instructions is executable according to a restricted register mode when the set of the instructions relate to one or more single function operations, wherein the restricted register mode includes only a single access or no access to a register. The method may further include executing, by an expression evaluator, operations of the set of the instructions related to the one or more single function operations, wherein the executing is performed in the restricted register mode and in parallel with the processor performing additional operations of the instructions.
Claims20
A method of computer processing, comprising:
- receiving instructions executable by a processor;
- determining, by the processor, that a set of instructions of the received instructions is executable according to a restricted register mode in which the set of instructions relate to one or more single function operations that require no access to a register during execution of the one or more single function operations;
- and
- executing, by an expression evaluator, operations of the set of instructions related to the one or more single function operations, wherein the executing is performed in the restricted register mode and in parallel with the processor performing arithmetic logic unit (ALU) operations of the instructions.
A computer system, comprising:
- a processor;
- and
- an expression evaluator coupled with the processor and configured to:
- receive a first set of instructions from the processor, the first set of instructions executable according to a restricted register mode in which the set of instructions relate to one or more single function operations that require no access to a register during execution of the one or more single function operations;
- execute operations of the first set of instructions in the restricted register mode and in parallel with the processor executing operations of a second set of instructions;
- and
- send a final result to the processor based on the executed operations of the first set of instructions.
A computer-readable storage medium storing instructions for computer processing, the instructions executable by one or more processors, comprising:
- at least one instruction for causing a processor to receive restricted register instructions executable by a processor;
- at least one instruction for causing the processor to determine that a set of instructions of the restricted register instructions is executable according to a restricted register mode in which the set of instructions relate to one or more single function operations that require no access to a register during execution of the one or more single function operations;
- and
- at least one instruction for causing the processor to execute operations of the set of instructions related to the one or more single function operations, wherein the executing is performed in the restricted register mode and in parallel with the processor performing additional operations of the restricted register instructions,
- wherein the executing is performed in the restricted register mode and in parallel with the processor performing additional operations of the restricted register instructions.
Dependencies are inferred from the claim text.